Arm Debuts eMRAM IoT test chip with Samsung, Cadence

May 15, 2019

Arm Debuts eMRAM IoT test chip with Samsung, Cadence

The Musca-S1 test chip and an accompanying development board enable IoT SoC designers to evaluate eMRAM technology, which can scale below 40 nm to support a range of memory and power requirements.

SAMSUNG FOUNDRY FORUM. Arm, Samsung Foundry, Cadence, and Sondrel have collaborated on the Musca-S1, a 28 nm fully-depleted silicon-on-insulator (FD-SOI) embedded MagnetoResistive RAM (eMRAM) test chip based on Arm Cortex-M33 IP. The Musca-S1 test chip and an accompanying development board enable IoT SoC designers to evaluate eMRAM technology, which can easily scale below 40 nm to support a broad range of memory and power requirements.

The Musca-S1 test chip combines on-chip power control, eMRAM non-volatile memory power shutdown, and Samsung’s FD-SOI body biasing process for highly energy-efficient IoT device prototyping. The IP was implemented using Cadence Verification Suite and DFM signoff tools.

The chip has been certified to Level 1 of Arm’s Platform Security Architecture, integrating Arm CryptoCell-300 technology, Arm Coresight, Arm TrustZone, and Trusted Firmware-M (TF-M). The test chip is capable of running Arm’s Mbed OS, while device and data management capabilities can be tested using Arm’s Pelion IoT platform.

The Musca-S1 test chip and accompanying development board will be available in limited quantities beginning in Q3 2019.

More information is available at www.arm.com/products/development-tools/development-boards/musca-a1-iot.

 

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