SmartDV Delivers First-to-Market MIPI A-PHY v1.0 Verification IP

By Tiera Oliver

Associate Editor

Embedded Computing Design

October 05, 2020

News

SmartDV Delivers First-to-Market MIPI A-PHY v1.0 Verification IP

A configurable bus functional model (BFM), protocol monitor, and library of integrated protocol checks come standard with SmartDV's Verification IP.

SmartDV Technologies is the first company to ship Verification intellectual property (IP) to support MIPI A-PHY v1.0, the industry-standard, long-reach serializer-deserializer (SerDes) physical layer interface, delivering it as the MIPI Alliance announced availability.

MIPI A-PHY v1.0's asymmetric long-reach physical layer interface forms the cornerstone of the MIPI Automotive SerDes Solutions (MASS) that provide connectivity for Advanced driver-assistance systems (ADAS), in-vehicle infotainment (IVI), and other surround-sensor applications. 

According to the company, with all SmartDV configurable and reusable plug-and-play Verification IP, users get to market ideally and confidently. The MIPI A-PHY v1.0 Verification IP can be used throughout a coverage-driven chip design verification flow in simulation, emulation, and field programmable gate array (FPGA) prototyping. It also features SimXL, Synthesizable Transactors for accelerating system-level, system-on-chip (SoC) testing on hardware emulators, or FPGA prototyping platforms. SimXL allows early software development on an FPGA platform, as well as ideal porting of simulation tests to emulators and FPGA platforms.

A configurable bus functional model (BFM), protocol monitor, and library of integrated protocol checks come standard with SmartDV's Verification IP. The IP supports all major verification languages and methodologies, including the open verification methodology (OVM), universal verification methodology (UVM), and SystemC.

The SmartDV MIPI A-PHY v1.0 Verification IP is available now and backed by an experienced R&D team that works individually with each user installation. Advanced configuration and status reporting interfaces are supplied, along with a comprehensive test suite that can be implemented in ASIC, SoC, or FPGA designs.

Pricing is available upon request. Fast turnaround customization is available.

For more information, visit: http://www.smart-dv.com/

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SmartDV? Technologies

77 North Almaden, Suite 1718
San Jose, CA 95110

Tiera Oliver, Associate Editor for Embedded Computing Design, is responsible for web content edits, product news, and constructing stories. She also assists with newsletter updates as well as contributing and editing content for ECD podcasts and the ECD YouTube channel. Before working at ECD, Tiera graduated from Northern Arizona University where she received her B.S. in journalism and political science and worked as a news reporter for the university’s student led newspaper, The Lumberjack.

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